Multi-functional systolic array with reconfigurable micro-power processing elements

This paper presents the design and implementation of high performance bi-directional linear systolic array (BLSA) with low-power, reconfigurable processing elements (PE). The BLSA acts as a hardware accelerator for implementing a broad class of problems which are met in a variety of applications such as digital signal processing, computer graphics, graph algorithms, etc. We define a unique algorithm representation for solving problems such as matrix multiplication, transitive closure, finding critical path in a graph, finding all-pairs shortest paths in a graph, etc. The algorithm is mapped into a BLSA with reconfigurable PEs. A clock gating technique is used to minimize power-consumption of a multi-functional PE. Performance of the BLSA are considered from the aspects of power-consumption and communication bandwidth. Using clock gating technique we achieve PE power reduction of 85% in average. Communication bandwidth is considered for different number of PEs in the BLSA and different operand size. The obtained results are in the range of 442 up to 9460 MB/s, i.e. bandwidth of our design is better for larger array and operand size. A lower-power, reconfigurable PE is realized using Xilinx FPGA chips.