Board level drop test and simulation of leaded and lead-free BGA-PCB assembly

Leaded and lead-free ball grid array (BGA) components were tested in board level drop test defined in the Joint Electron Device Engineering Council (JEDEC) standard under different load levels. Finite element analysis (FEA) models were established using ANSYS. The stress and strain in the solder joint and the average strain energy density (SED) in the solder–pad interface accumulated in one cycle were calculated using ANSYS/LS-DYNA explicit solver. The results of experiment and simulation were employed to re-calculate the constants contained in the Darveaux model to extend its application to the drop test. Then, FEA models with different height and pitch of solder joints were established to obtain the SED to calculate the fatigue life of solder joint under different geometrical conditions through this modified model. The experiment and simulation reveal that the failures mainly occur in the solder–PCB interface in lower load level, the other way round, in a higher load level, the cracks are more possibly formed in solder–package interface; comparing to dropping in horizontal direction with package faces down, the solder joints are much harder to fail when dropping in vertical direction; An optimal height and smaller pitch of solder joints lead to lowest SED and best reliability in the drop test.