FPGA-based digital overcurrent relay with concurrent sense-process-communicate cycles

Communication between relays and the central control station is an important aspect of Special Protection Schemes (SPS) used in modern power systems. The relays are expected to perform sense-process-communicate cycles. A sequential implementation of these tasks increases the computational time and adversely affects the overall performance of the relay. This paper presents the design and hardware implementation of an overcurrent relay on Field Programmable Gate Array (FPGA) with concurrent sense-process-communicate cycles. The implementation is based on parallel pipelined architecture where sampling, measurement, processing and communication tasks are done concurrently. The relay is implemented on Xilinx Virtex-II Pro XC2VP30-FF896-7C FPGA Board. The proposed relay conforms to IEEE standard C37.112-1996 for overcurrent relays in power systems. It is equipped with serial/IP communication capability. The details of the hardware design, implementation and experimental test results on a hardware simulator of a 360 km transmission line are presented in this paper. The architecture provides a platform for implementing special protection schemes in power systems.