Study of capacitance nonlinearity in nano-scale multi-stage MOSFET-only sigma-delta modulators

Digital integrated circuits (ICs) can be integrated in low-cost digital CMOS technologies with less number of masks than a mixed-signal CMOS technology. This property, however, limits the access to reliable analog components such as linear capacitors and linear inductors. Regardless of the CMOS process, sigma-delta (ΣΔ) modulation of analog signals can be fulfilled by using ordinary MOS devices as capacitors. Called as MOS capacitors (MOSCAPs), these elements illustrate nonlinear C-V characteristic, although the thin gate oxide layer results a high capacitance per unit area. In this article, we investigate the effect of MOS capacitance nonlinearity on the overall performance of discrete-time sigma-delta modulators. To this end, a behavioral-level model of a MOSFET-only switched-capacitor (SC) integrator is proposed, and enables characterizing the transfer behavior of MOSFET-only modulators. The proposed model is used to analyze the linearity and to select a suitable architecture for the modulator. It helps to decide proper structure of each MOSCAP depending on its significance on the output linearity. In virtue of the new model, behavioral-level simulation of a 1-V 12-bit 20MS/s MOSFET-only 2 + 2 sturdy MASH (SMASH) modulator matches well to circuit-level simulations in 90-nm digital CMOS technology. For a −1.4 dB, 19.7 kHz input and an oversampling ratio of 16, the modulator achieves over 72 dB signal-to-noise plus distortion ratio (SNDR), only 3 dB lower than a conventional design based on linear metal-insulator-metal (MIM) capacitors.