Multi-phase low-noise digital ring oscillators with sub-gate-delay resolution

Multi-phase oscillators are often required to generate multiple clock phases with high frequency, high resolution and low-phase noise. This paper deals with self-timed ring oscillators (STROs), which are a promising solution for designing multi-phase clock generators. In STROs, the phase resolution can be adjusted as fin as desired by simply increasing its number of stages without frequency drop, and this resolution is not limited by the gate delay. In addition, different oscillation frequencies can be obtained by the same STRO depending on its initialization. Thanks to this configurability, 1/N (-10·log(N)dB) phase noise reduction is obtained at the cost of higher power consumption when the number of stages is increased N times, while keeping the same oscillation frequency. Moreover, clock jitter in STROs is reduced to the minimum and unavoidable component due to the white noise. Two test-chips have been designed and fabricated in STMicroelectonics CMOS 65 nm and in AMS 350 nm. Most of the measurements are perfectly in accordance with our theoretical claims.