High-Speed Virtual Logic Network on Chip Router Architecture for Various Topologies

Due to numerous complex routing links, traffic congestion and latency becomes an important issue in advanced Network on Chip (NoC) architectures. For this, we propose High-Speed Virtual Logic Network on Chip router architecture (HSVLN) for controlling the traffic congestion and deadlock issues, and High-Speed Routing Algorithm (HSRA) that can reduce the latency by selecting the minimal interval paths. When we analyze the HSVLN for various topologies, its performance seems to be 50% better than existing router architectures. In reality, HSRA incorporates with HSVLN and it is examined with all proposed topologies such as the 2D-Global Mesh over Local Mesh (GMoLM), 3D-Mesh and 3D-Torus. Simulation and synthesis results of HSRA carried out by using Xilinx 14.7 and targeted on the Vertex-7 FPGA. We have analyzed the performance of HSRA for all proposed topologies, and their results are manifested by measuring with respect to latency and throughput. 2D-GMoLM showing an average reduction of latency by 3/5 times, enlarging the area by 1/4 and an increase in throughput by 1/3 times compared with 3D-Mesh and 3D-Torus. Therefore, when we compared with other two topologies, HSRA showed an adequate performance in 2D-GMoLM.