A Spiking Neural Network implemented with Single-Electron Transistors and NoCs

This work proposes a Spiking Neural Network, SNN, based on a nanoelectronic spiking neuron - as building block - and a 2D-mesh network-on-chip, NoC - as interconnect architecture. The SNN obtained from the NoC is an alternative for high density architectures, providing reconfigurability, high scalability and low power consumption. A look-up table router was used to connect all units. Further on, the eXclusive-OR, XOR, benchmark problem was used to validate the functionality of the nanoelectronic SNN.