Impact of Cache Voltage Scaling on Energy-Time Pareto Frontier in Multicore Systems

High performance computing centers need to keep up with the growing workload of varying computational characteristics. Due to their high computation rates, these computing systems consume vast amounts of energy with increasing electricity costs. As an approach to balancing computation demand with energy consumption, state-of-the-art dynamic voltage and frequency scaling (DVFS) methodologies are used for improving the energy efficiency of computing systems. However, these studies often do not explore the extent to which their solutions are close to theoretically optimal limits. This work formulates optimal boundaries for energy-time performance with a Linear Programming (LP) approach. The formulation utilizes per-core energy consumptions and execution times obtained during the profiling phase to optimize the voltage and frequency (V/F) level assignments at runtime. For each of the four benchmarks considered in this work, the optimized V/F assignments are used to bound Pareto frontiers, which trade off energy consumption and execution time. In particular, this work studies the impact of scaling the voltage and frequency of the cache subsystem in a multicore system on establishing the energy-time Pareto frontier. An unexpected result of our study is that when the frequencies of caches are not scaled with that of the cores (i.e., fixed at 2.0 GHz), the proposed LP-based technique improves the overall Energy-Delay-Product (EDP) as much as 35% compared to the traditional no-DVFS Pareto frontier. Furthermore, this work compares the performance of three heuristic-based energy-efficient DVFS algorithms to demonstrate the differences between heuristics performances and the LP-based optimal Pareto frontier.