Impact of geometric, thermal and tunneling effects on nano-transistors

Electronic transistors are fundamental building blocks of large scale integrated circuits in modern advanced electronic equipments, and their sizes have been down-scaled to nanometers. Modeling and simulations in the framework of quantum dynamics have emerged as important tools to study functional characteristics of these nano-devices. This work explores the effects of geometric shapes of semiconductor-insulator interfaces, phonon-electron interactions, and quantum tunneling of three-dimensional (3D) nano-transistors. First, we propose a two-scale energy functional to describe the electron dynamics in a dielectric continuum of device material. Coupled governing equations, i.e., Poisson-Kohn-Sham (PKS) equations, are derived by the variational principle. Additionally, it is found that at a given channel cross section area and gate voltage, the geometry that has the smallest perimeter of the channel cross section offers the largest channel current, which indicates that ultra-thin nanotransistors may not be very efficient in practical applications. Moreover, we introduce a new method to evaluate quantum tunneling effects in nanotransistors without invoking the comparison of classical and quantum predictions. It is found that at a given channel cross section area and gate voltage, the geometry that has the smallest perimeter of the channel cross section has the smallest quantum tunneling ratio, which indicates that geometric defects can lead to higher geometric confinement and larger quantum tunneling effect. Furthermore, although an increase in the phonon-electron interaction strength reduces channel current, it does not have much impact to the quantum tunneling ratio. Finally, advanced numerical techniques, including second order elliptic interface methods, have been applied to ensure computational accuracy and reliability of the present PKS simulation.