Improvement of SiO2/4H-SiC Interface properties by post-metallization annealing

Electrical characteristics of SiC metal-oxide-semiconductor (MOS) capacitors with atomic-layer-deposited SiO2 (ALD-SiO2) gate dielectrics were investigated. Post-metallization annealing (PMA) with W gate electrodes at 950 °C showed a large recovery in the flatband voltage toward the ideal value and the hysteresis was reduced to 36 mV. Interface state density (Dit) of 3 × 1011 cm−2/eV was obtained after the PMA for 5 × 103 s. The concentration of the residual carbon atoms in the SiO2 gate dielectrics has been reduced after annealing, suggesting one of the possible origins of the improvements.