Location resolved transient thermal analysis to investigate crack growth in solder joints

Solder joint cracking is a common failure mechanism in microelectronic packages. To investigate interconnect integrity and reliability different inspections are established with their strengths and weaknesses: X-ray, scanning acoustic microscopy (SAM), Infrared (IR)-Thermal Imaging as well as Transient Thermal Analysis (TTA). TTA is well suited to detect changes in the thermal path, i.e. delamination in a package. However, spatial resolution in plane of an interconnection is restricted. Still, spatial resolution is necessary to analysis the crack growth in solder joints. In addition the local temperature strongly depends on the local position of a bad thermal contact. In the paper an innovative new test method, location resolved transient thermal analysis (LrTTA), is developed and its potential is investigated. LrTTA is based on transient thermal measurement (TTM). It uses several distinct diodes on a test chip to detect the thermal performance of interfaces and assemblies. The temperature is measured by the forward voltage as a function of time at different locations on the chip. Spatial resolution is obtained, e.g. cracks, voids and thickness variations can be resolved in the interface. For first experimental application of the method, a silicon thermal test chip with four differently located diodes was employed. The test chip was soldered onto an Aluminium Insulated Metal Substrate (Al-IMS) and exposed to temperature cycles. TTM were performed directly after assembly and after specific temperature shock cycle numbers (− 40 °C/+125 °C). After data processing, the increase of the thermal impedance of each diode between the initial “0” cycles and “n” cycles was obtained. The thermal data are correlated with void formation detected by X-ray. Crack or delamination is in addition detected with scanning acoustic microscopy (SAM). As a quantitative analysis, a finite element (FE) model was set up and applied to analyze the solder joint with and without voids and also the crack propagation in the solder joint during temperature shock testing. Based on the FE modelling, the thermal influence of voids can be calculated and thus these voids can be detected. Further, based on the numerical analysis, crack size and location can be identified.