The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system

In the nanoscale regime, the aggressive scaling of devices is affected by several severe reliability issues, including negative bias temperature instability (NBTI) and gate oxide breakdown (GOBD). Generally, the mathematical models of NBTI and GOBD are derived from device level test structures with accelerated tests. However, although both models are highly dependent on temperature and the gate voltage and both mechanisms are based on the probability of trap generation in the oxide layer, each model has a different impact on circuit performances. In this paper, we use a physical probability model of trap generation for both mechanisms. We first simulate the impact on circuits using process models involving threshold voltage shifts and gate oxide leakage currents for NBTI and GOBD, respectively. Then, we find a relationship between the model parameters and power/ground signal degradation. We find the stress conditions that make each of the two mechanisms dominant in the power/ground signal. We calibrate the NBTI and GOBD model parameters of each chip to experimental results. Hence, it becomes possible to identify chips that are more or less vulnerable to NBTI and GOBD.