Wire width dependence of hot carrier degradation in silicon nanowire gate-all-around MOSFETs

The increase of hot carrier degradation with decreasing wire width in nanowire gate-all-around (GAA) MOSFETs has been investigated through experiment and device simulation. From the systematical analysis of measurement and simulation, it is found that the increase of device degradation in narrow devices is dominantly governed by the increased current density, the large lateral and vertical fields, and the increased interface state generation rather than by the reduced floating body effects. The more significant hot carrier degradation with decreasing wire width is likely to be proportional to the surface-to-volume ratio of nanowires.