Optimization of a MOS-IGBT-SCR ESD protection component in smart power SOI technology

A MOS-IGBT-SCR component that was proposed in a previous paper to increase the device robustness and the cost of ESD protection circuit is optimized in this paper. In order to improve its latch-up immunity, several variations of geometrical parameters that have been simulated using TCAD Sentaurus Device in another previous paper have been implemented and compared in this work. The drift area, the form factor, and the proportion of P+ sections inserted into the drain are the main parameters, which have a significant impact on the latch-up immunity. TLP characterization, and curve tracer measurements have been carried out to evaluate the proposed solution. Holding current increases up to 70 mA and holding voltage up to 10 V.