Solder void position and size effects on electro thermal behaviour of MOSFET transistors in forward bias conditions

This research aims to enhance the understanding on position and size effects on the electro thermal behaviour of low voltage power MOSFET transistors in forward bias condition. The numerical simulations are based on a fractional design of experiments (DoE). The performance of a finite elements model is discussed by comparing thermal and electrical measurements to results of finite elements simulation on a module of free void and voided solder. The void in the model is afterwards parameterized on position and size, according to the fractional DoE of the study. The combined functions issued from the parametric simulations and the DoE show the main impact of void size on temperature of the device and on the surface temperature of the bonding wires. From the numerical viewpoint, the most impacting position of void depends highly on the void size. The redistribution of current density and temperature on MOSFET chip and bonding wires due to solder void is also observed. A future experimental study in respect to the same DoE is expected in prospect, in order to fulfil the complementarity for this approach.