Context aware slope based transistor-level aging model

Accurate age modeling, and fast, yet robust reliability sign-off emerged as mandatory constraints in IC design for advanced process technology nodes. This paper proposes a device-level aging assessment and prediction model using the signal slope as aging quantifier, that accounts not only for the intrinsic self-degradation but also for the influence of the surrounding circuit topology. Experimental results indicate the validity of slope as aging quantifier and that aging is underestimated when topology influence is disregarded.