Reliability investigation of the degradation of the surface passivation of InAlN/GaN HEMTs using a dual gate structure

We analyze the degradation of InAlN/GaN HEMTs using a secondary gate electrode placed on top of the SiN passivation layer in between the Schottky gate and drain contact. Although the actual transistor showed only minor degradation during the stress test under off-state bias for more than 60 h, a linear increase of trapped charges in the SiN layer has been detected starting at about 13 h of stress. The charge increase is correlated with the increased leakage current and dielectric breakdown at the secondary gate.