Positive bias temperature instabilities on sub-nanometer EOT FinFETs

► PBTI was measured on low EOT triple gated FinFETs with TiN/HfO gate stack to assess their reliability. ► TiN gate reduces SiO interlayer and increases PBTI degradation. ► Wider devices present a higher degradation which may be caused by a higher density of defects on the top-wall. ► PBTI degradation could be a problem for ultra low EOT for both planar and FinFET devices.