A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32Â nm node

The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such as the CMOS 32 nm in this work. This paper presents a local ESD protection structure based on dynamic triggered SCR and qualifies through TLP and vf-TLP for GO1 = 1 V and GO2 = 1.8 V power domain.