Failure analysis defect location on a real case 55Â nm memory using dynamic power supply emulation

► Defect location techniques in failure analysis of CMOS 55 nm SRAM failure. ► Additional signatures obtained by applying a clock signal on the circuit power supplies. ► More information on the defect location using dynamic power supplies test. ► Original circuit emulation opening the door to more location techniques. ► New axis of development in circuit debug in failure analysis.