Time-to-digital-converter based on multiple-tapped-delay-line

The TDC consists of measurement-module and the program run on a personal-computer. The measurement-module has been implemented into field-programmable-gate-array (FPGA) Xilinx Virtex 5 device. It consists of 125 of 32-bit tapped-delay-lines (TDL) of about 323ps equivalent-bin-width on average. The idea of measurement consists in combining all 125 TDL results into one high-precision TS for every hit. Mathematical analysis necessary to perform this operation is described in details. Two methods of finding offsets between TDLs are presented. The measurement-results are presented as TI histograms and TDC characteristics. Owing to high relative non-linearity of TDC characteristic the quantisation-and-non-linearity-minimisation (QNM) method of TI histogram calculation turned out to be very useful.