کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
7195300 | 1468200 | 2018 | 16 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
SEU emulation in industrial SoCs combining microprocessor and FPGA
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی مکانیک
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چکیده انگلیسی
FPGAs (Field-Programmable Gate Array) and FPGA-based SoCs (System-on-chip) are electronic devices which offer high computational performance and low time-to-market for low and medium production volumes. They are gaining popularity in critical sectors, such as automotive, aerospace, avionics and railway, making their reliability evaluation mandatory. FPGAs are notoriously sensitive to SEUs (Single Event Upsets), which are random memory errors provoked by radiation particles. The failure rate of an FPGA varies with the implemented design, depending on the amount of used resources and the implemented redundancy schemes among others. FPGA-based circuits are being used in complex safety-critical engineering systems that are designed in compliance with dependability regulations. This work presents an emulation-based methodology for estimating the failure rate of designs implemented in FPGA SoCs, which is a key data in this scenario.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Reliability Engineering & System Safety - Volume 170, February 2018, Pages 53-63
Journal: Reliability Engineering & System Safety - Volume 170, February 2018, Pages 53-63
نویسندگان
Igor Villalta, Unai Bidarte, Julen Gómez-Cornejo, Jaime Jiménez, Jesús Lázaro,