SYNTHESIS OF PARALLEL CONTROLLERS THROUGH A LOGIC MATRIX MODEL

This paper gives a brief summary of the studies carried out about how to implement parallel logic controllers in reconfigurable circuits of the FPGA (Field Programmable Gate Array) kind. The necessity to base it on a mathematical model which is easily joined to the graphic editor of the designs and to the VHDL description is focused on. Also the necessity to obtain a surround of automatic systems development which integrates all the necessary elements in order to automate the whole process of development, debugging, configuration and verification is discussed. In this way a realistic system with a practical application has been achieved. The descriptive part of this study is focused on the description of the model, its validation, using an example and its test, using simulation. Finally, a system integrating all elements is described.