کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
728758 | 892850 | 2007 | 12 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Caliper rule based ADC architectures
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
کنترل و سیستم های مهندسی
پیش نمایش صفحه اول مقاله
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چکیده انگلیسی
In this paper, a new kind of architectures for the full-flash or subranging Analogue to Digital Converters (ADC's) is presented. To describe these architectures and explain the intrinsic conversion procedure, we refer to a technique, already presented by the author, which improves the accuracy of a measurement system. This technique is based on the arithmetic of the integer numbers in finite fields and include, as a particular case, the well known “caliper rule”. The said technique is recalled and explained by using some simple measurement examples, in particular length, time and mass measurements. Then the technique is applied to the full-flash and subranging ADC architectures, greatly reducing the number of the resistors necessary to generate the voltage reference scale. Indeed, the required resistors for a n-bits conversion word length are reduced from 2n to about 3â2n/2. This reduction and the particular comparison method involved in the theory allow the realization of full-flash architectures having large word lengths.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Measurement - Volume 40, Issue 5, June 2007, Pages 479-490
Journal: Measurement - Volume 40, Issue 5, June 2007, Pages 479-490
نویسندگان
Roberto Lojacono,