FPGA implementation of a delay-line readout system for a particle detector

We describe a novel Time to Digital Conversion (TDC) architecture implemented in an FPGA (Field Programmable Gate Array). FPGA technology was employed due to its development flexibility and low cost. The various concepts investigated and tested are application specific. An FPGA is used to measure and code the time difference between two input pulses. The time measurement incorporated floorplanning and the manual placing of propagation delay elements (delay chains) inside the chip to mimic a real passive delay-line. Tests employing simulated passive analogue delay-line circuits and results using real passive delay-lines have produced very encouraging results. Pending some more testing this design practice will be used for a space instrumentation application due for launch in 2006.