FPGA implementations of an ADALINE adaptive filter for power-line noise cancellation in surface electromyography signals

This paper presents FPGA implementations of an adaptive linear neural network (ADALINE) based adaptive filter for power-line noise cancellation in surface Electromyography (sEMG) signals. 10-Tap ADALINE filters in the 16-bit Q0.15 fixed-point format are offered into two categories: small area implementations and high-throughput implementations. The small area ones are optimized by using the resource-sharing technique that considers the interconnect complexity. For the high-throughput ones, we propose the delayed ADALINE (DADALINE) pipelined adaptive filter which is based on the relaxed look-ahead technique. The implementation results on the Xilinx XC3S1200E-4FG320 FPGA show that the smallest implementation achieved the throughput of 1.61 million samples per second (MSPS) and the area of three multipliers, 611 LUTs, and 511 flip-flops, and the fastest implementation achieved 56.15 MSPS and the area of 23 multipliers, 945 LUTs, and 907 flip-flops. Each implementation has been tested on an FPGA board interfaced with an sEMG measurement set.

► We propose FPGA implementations of a 10-tap ADALINE based adaptive filter for power-line noise cancellation in sEMG signals.
► The filters are in the standard 16-bit fixed-point Q0.15 format.
► The interconnection minimized resource-sharing has been applied to optimize the area.
► The pipelined implementations, called DADALINE, also have been proposed for high throughput.
► The test results on our sEMG measurement set verify the validity of the proposed implementations in real-time applications.