The top-down fabrication of a 3D-integrated, fully CMOS-compatible FET biosensor based on vertically stacked SiNWs and FinFETs

• A high density vertically stacked SiNW and FinFET with ultra-thin (15–30 nm) and long structures has been fabricated successfully.
• 3D devices features highly robust stacked structures for biosensor applications.
• Fully top-down CMOS compatible process introduced.
• Sensor can be integrated heterogeneously.

A 3D vertically stacked silicon nanowire (SiNW) and Fin field effect transistor (FET) featuring a high density array (7 or 8 × 20 SiNWs, >4 Fins vertically stacked) of fully depleted, ultra-thin (SiNWs diameters ∼15–30 nm, Fin width/height fw ∼30 nm/fh ∼150 nm), long (>2 μm) and suspended channels has been successfully fabricated for the first time by a top-down, complementary metal oxide semiconductor (CMOS) compatible process on silicon on insulator (SOI) substrates for biosensing applications. SiNW and FinFETs continue to draw interest as biological sensors for their outstanding sensitivity due to their large surface to volume ratios (S/V), high selectivity towards a myriad of analytes through surface functionalization and the possibility for label free, direct monitoring of biological activities. In this paper we describe different strategies and limitations for the successful development and fabrication of a 3D Si nanostructure FET using conventional clean-room fabrication techniques and their integration into heterogeneous systems. The vertical stacking allows for higher utilization of the Si substrate, high output currents (1.3 mA/μm, normalized to a NW diameter of 30 nm at VSG = 3 V, and Vd = 50 mV, for a standard structure with 7 × 10 NWs stacked) and high chances for biomolecule interaction as the number of conduction channels increases. Also, as the NWs/Fins are suspended, their entire surface area is exposed to the sensing analyte. The configuration of the 3D sensor furthermore offers excellent electrostatic control of the channels by the possibility of applying symmetric or asymmetric gate potentials to tune the sensitivity and optimize the power consumption. Our fabrication scheme is competitive in terms of scaling and NW density in comparison to bottom-up and other top-down approaches with the advantage of using a CMOS-compatible, high yield (>90%), reproducible and robust processes.