A grinding-based manufacturing method for silicon wafers: generation mechanisms of central dimples on ground wafers

Silicon wafers are the fundamental building blocks for most integrated circuits. The lapping-based manufacturing method currently used to manufacture the majority of silicon wafers will not be able to meet the ever-increasing demand for flatter wafers and lower prices. A grinding-based manufacturing method has been investigated experimentally to demonstrate its potential to manufacture flat silicon wafers at a lower cost. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. This paper, as a follow up, addresses one of the reasons for the poor flatness at the wafer center: central dimples on ground wafers. A finite element model is developed to illustrate the generation mechanisms of central dimples. Then, effects of influencing factors (including Young's modulus and Poisson's ratio of the grinding wheel segment, dimensions of the wheel segment, grinding force, and chuck shape) on the central dimple sizes are studied. Pilot experimental results will be presented to substantiate the predicted results from the finite element model. This provides practical guidance to eliminate or reduce central dimples on ground wafers.