The Investigation of a SOI-LDMOS Equipped with the Poly-PiN-diode Field Plate

We utilize the electric peak field at the PN junction of a Poly-PiN-diode to optimize the potential distribution for a thin-SOI-layer LDMOS. The location and the height of the peak field is free to be set at any position and value along the drift region by adjusting the doping profile in the polysilicon. Therefore, the Poly-PiN-diode allows excellent flexibility for device potential optimization compared to conventional means. As the polysilicon can be directly deposited on the dielectric, the fabrication for the device is feasible and the high-K material other than SiO2 is available for the dielectric material for further device performance improvements. The optimization of an LDMOS with SOI layer thickness of 1.5 μm by the Poly-PiN-diode is discussed in this letter, the numerical simulation results indicated that the breakdown voltage (BV) increases by 42% and the specific on-resistance decreases by 60% compare with those of the conventional SOI-LDMOS under the condition of SiO2 dielectric. The BV is further increased with the HfO2 or PZT dielectric, which are 51% and 67%, respectively. Moreover, there is no compromising of the switching behaviour and gate leakage current for this novel device.