Implementation of the VMM ASIC in the Scalable Readout System

We report on the implementation of the VMM in the Scalable Readout System carried out by the RD51 collaboration in the framework of a detector project related to the European Spallation Source ERIC. Due to the hierarchical design of the Scalable Readout System, only specific parts of the readout chain need to be adapted or designed, which is the carrier board for the front-end chip, an adapter card that connects to the common hardware of the system and the firmware for a field programmable gate array. In addition, we have developed dedicated software for slow control, data acquisition and online monitoring. The readout system has been tested in the laboratory and in particle beams and we present results which proof the functioning of the system, even though it is still in a prototype state.