کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
8173220 | 1526340 | 2015 | 9 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Design of a 12-bit 1Â MS/s SAR-ADC for front-end readout of 32-channel CZT detector imaging system
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
فیزیک و نجوم
ابزار دقیق
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
A 12-bit 1MS/s SAR-ADC for the front-end readout of a 32-channel CZT detector imaging system is presented. In order to improve the performances of the ADC, several techniques are proposed. First, a novel offset cancellation method for comparator is proposed, in which no any capacitor is introduced in the signal pathway, thus it has faster operation speed than traditional one. Second, the architecture of unit capacitor array is adopted in the charge-redistribution DAC to reduce the capacitor mismatch. Third, the radiation-hardened ability is enhanced through circuit and layout design. The prototype chip was fabricated using a TSMC 0.35Â um 2P4M CMOS process. At a 3.3/5Â V power supply, the proposed SAR-ADC achieves 67.64Â dB SINAD at 1MS/s, consumes 10Â mW power and occupies a core area of 1180Ã1080Â um2.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment - Volume 786, 21 June 2015, Pages 155-163
Journal: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment - Volume 786, 21 June 2015, Pages 155-163
نویسندگان
Wei Liu, Tingcun Wei, Bo Li, Panjie Guo, Yongcai Hu,