The Immunity of Evolvable Digital Circuits to ESD Interference

With the rapid development of semiconductor technology and the increasing proliferation of emission sources, digital circuits are frequently used in harsh and hostile electromagnetic environments. Electrostatic Discharge (ESD) interferences are gradually gaining prominence, resulting in performance degradations, malfunctions and disturbances in component and/or system level applications. Conventional solutions to such problems are shielding, filtering and grounding. This paper proposes a novel Evolvable Digital Circuit (EDC) for intrinsic immunity. The key idea is motivated by the noise-robustness and fault-tolerance of the biological system. First, the architecture of the EDC is designed based on the cell structure. Then, ESD immunity tests are carried out on the most fragile element of the EDC in operation. Based on the results, fault models are also presented to simulate different functional disturbances. Finally, the immunity of the EDC is evaluated while it is exposed to a variety of simulated environments. The results which demonstrate a graceful immunity to ESD interference are presented.