Transition Analysis for Power Reduction in SoC

Size and complexity have been major issues for System-on-a-Chip (SoC) testing. Transition analysis plays a significant role in power consideration of SoC testing. Transition is directly propositional to the power. This paper is based on finding transition calculation to achieve minimum power consideration. Transition study is applied for both specified and unspecified bits. The unspecified bits are specified by using X filling techniques like Zero filling and One filling algorithm. Transition analysis is considered for different partition length. The proposed method is successfully tested on ISCAS89 benchmark circuits which achieve minimum power consideration