An Optimized Network-on-Chip Design for Data Parallel FFT1

In this paper, we propose an optimized Network-on-Chip (NoC) design for data parallel FFT applications. NoC based architecture is proposed for future multicore processors due to its scalability. FFT is widely used in digital systems. The implementation of FFT on conventional architectures have been studied. However, the evaluation of data parallel FFT in a NoC platform has not been well addressed. We analyse data parallel FFT in terms of traffic patterns and propose an optimized NoC design. Experiments show that, the execution time of our optimized design is 12.13% faster than the original.