Adapting Scan Based Test Vector for Compression Method Based On Transition Technique

Present complexity of System on Chip (SoC) design is increasing rapidly in the number of test patterns, huge switching activity and its transition time. This large test data volume is becoming one of the major problems in association with huge switching activity and its corresponding response time. This paper considers the problem of huge test pattern in scan based design. This proposed algorithm is based on reducing test pattern on scan shift in operation. This is achieved by identifying test data transition and equally segmenting the scan based test patterns. Each scan test pattern is considered by its transition and segmented into equal necessary blocks. This finally gives the compressed test patterns in reduced test patterns. Theoretical analysis and experimental results on ISCAS89 shows that the proposed method reduces test pattern by 37% when compared to the traditional approaches.