SEU Tolerance Design And Implementation of A Space High Reliability Microprocessor

This paper focuses on study of a space high reliability microprocessor which is designed for space platforms, such as on-board computer systems. Space radiation environment is a special factor that should be considered when we design space high reliability processor. The architecture of Leon 3 microprocessor is investigated, which conforms to the IEEE-1754 (SPARC V8) architecture. Single-Event Effect of Leon3 is analyzed. Based on Leon3, a fault tolerance microprocessor is designed to verify Single Event Upset tolerance efforts. Expansion Hamming Code is adopted by IU and CRC is adopted by Cache to avoid some magnitude of SEU error to some degree. Inject fault in Modelsim simulator is applied to verify fault tolerance design. An FPGA platform is built to evaluate the cost and compatibility of this fault tolerance design.