کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
865978 | 909690 | 2007 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Fault Tolerance Mechanism in Chip Many-Core Processors
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی (عمومی)
پیش نمایش صفحه اول مقاله

چکیده انگلیسی
As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors' yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors' performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Tsinghua Science & Technology - Volume 12, Supplement 1, July 2007, Pages 169-174
Journal: Tsinghua Science & Technology - Volume 12, Supplement 1, July 2007, Pages 169-174
نویسندگان
Zhang (å¼ ç£), Han (é©é¶å), Li (æåä¼), Li (ææç»´),