Simulation and implementation design of multi-mode decoder for WiMAX and WLAN applications

The need for achieving high data throughput with low hardware complexity for long haul communication systems is a challenging task. The emerging communication systems in recent times have benefited from the availability of multi-mode decoders which can achieve better error rate performance with reduced complexity under noisy channel conditions. This paper presents a low complex multi-mode decoder architecture for Wi-Max and WLAN applications. To achieve good error correcting performance with a better decoding stability, a modified optimally quantized offset min-sum decoding is adopted. By exploring the properties of the layered decoding scheme, an enhanced quasi-cyclic low-density parity-check (QC-LDPC) code with sub-matrix re-ordering and layered decoding scheme is employed to offer adequate flexibility for parallel degree optimization and convergence speed. This in turn reduces the linear encoding complexity and data correlation problems during the multi-mode operations of the proposed decoder. Furthermore, to reduce interconnect complexity and the critical path delay, a modified reconfigurable routing network is employed. The proposed multi-rate decoder is designed and implemented using 65 nm CMOS Technology to support all the modes of IEEE 802.11n and IEEE 802.16e applications. The implementation results show that the multi-mode decoder achieves good throughput-to-area ratio (TAR) with less power consumption when compared to other multi-mode decoders.