Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization

Also, an MPEG-2 codec implementation is presented for use in applications, where the video scalar and codec may be used to reduce transmission bit rate. Transmission of high resolution pictures of XGA format and above, even after effecting compression, demand very high serial channel bandwidth requirement, far exceeding the prescribed maximum by MPEG-2 standards. This can be circumvented by down scaling and then effecting compression before transmission, trading off for a little image quality, as presented in this paper.