Evaluation of parasitic capacitances for interconnection buses crossing in different layers

Analytical evaluation of capacitances of interconnections in VLSI circuits is based on empirical equations formulated for basic typical structures combined to model more complex geometric configurations. In this paper this procedure of addition of subregions contribution to the total capacitance is verified for lines crossing in several metallization levels. As a result of simulation experiments simplified but more accurate procedure of evaluation of this capacitance was proposed.