Ion implantation in advanced planar and vertical devices

The extent (“gate overlap”) and slope (“abruptness”) of the lateral junction are quickly replacing vertical junction depth as the most important physical junction metrics in advanced device architectures. This is in particular true for ultra-thin body devices, where the vertical junction is limited by a geometric constraint. The optimum gate overlap is quite small, or may even be negative, making a process without the need of high-tilt implantation feasible, even for dopant activation with negligible diffusion by flash annealing or laser thermal processing. Dopant activation by solid phase epitaxial regrowth might require high-tilt implants for a positive overlap. The use of such implants, however, is expected to lead to severe gate-poly and gate-oxide degradation. Scaling the 150 nm technology has drastically shrunk the overlap, accomplished by an equally aggressive reduction in thermal budget. For a 65 nm node device, a significant fraction of the overlap originates in the as-implanted dopant profile and the importance of diffusion is diminished. As a consequence small changes in the as-implanted profile are beginning to have a disproportionate impact on device characteristics. Small angular deviations of the incident beam from normal incidence, as seen by the wafer, lead to large changes in on-current. This can be alleviated significantly by a quad implant provided the tilt-angle is sufficiently large, in the order >5°.