A TCAD evaluation of a single Bulk-BICS with integrative memory cell

This work presents a new topology for a Bulk-Built-in Current Sensor (Bulk-BICS) in a circuit for monitoring the effects of single energetic particle strikes on PMOS and NMOS transistors. Several of these sensors may have their outputs grouped in parallel, increasing integration density, which reduces the area overhead for the proposed Bulk-BICS technique. The circuit was designed in a 40-nm technology node using circuit simulation and evaluated with transistor-level Technology Computer-Aided Design (TCAD) software.