Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates

In this paper, the concept of multi-objective optimization is introduced in the automation of the placement task in analog integrated circuits layout design. To bridge the difficulties found on state-of-the-art works on fulfilling proximity constraints, here, cells are organized into proximity groups which implement the desired set of symmetry and proximity requirements. Then, an innovative archived-based multi-objective simulated annealing algorithm, operating over an absolute representation, is proposed to optimize the placement of each proximity group. In contrast to traditional single-objective placement approaches, the resulting Pareto fronts of placements, representing the tradeoffs between the optimization objectives of each group, are combined, bottom-up, through the design hierarchy, until a final front is obtained. This way, the problem's complexity is reduced, and split over multiple executions of the optimization kernel with less design variables, and also, analog designer becomes aware of the design tradeoffs. The proposed multi-objective and hierarchical methodology was implemented, and, experimental results prove that previous efforts on single-objective absolute representations are no match for the obtained floorplans. Furthermore, the obtained Pareto fronts contain the solutions found with the most recent published topological representations for the well-known Microelectronics Center of North Carolina benchmark sets, and, allowed an improvement of placement area up to 23% on a previously optimized folded cascode operational amplifier for the United Microelectronics Corporation 0.13 μm fabrication process.