Delay bounds for FIFO aggregates: a case study

In a DiffServ architecture, packets with the same marking are treated as an aggregate at core routers, independently of the flow they belong to. Nevertheless, for the purpose of QoS provisioning, derivation of upper bounds on the delay of individual flows is of great importance. In this paper, we consider a case study network, composed by a tandem of rate-latency servers that is traversed by a tagged flow. At each different node, the tagged flow is multiplexed into a FIFO buffer with a different interfering flow. The tagged flow and the interfering flows are all leaky-bucket constrained at the network entry. We introduce a novel methodology based on well-known results on FIFO multiplexing from Network Calculus, by means of which we derive an end-to-end delay bound for tagged flow traffic. The delay bound assesses the contribution to the delay due to the interference of other flows precisely, and to the best of our knowledge, it is better than any other applicable result available from the literature. Furthermore, we utilize the delay bound formula to quantify the level of overprovisioning required in order to achieve delay bounds comparable to those of a flow-aware architecture.