کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
10364158 871469 2014 10 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications
چکیده انگلیسی
In this paper, an area efficient and high throughput multi-rate quasi-cyclic low-density parity-check (QC-LDPC) decoder for IEEE 802.11n applications is proposed. An overlapped message passing scheme and the non-uniform quantization scheme are incorporated to reduce the overall area and power of the proposed QC-LDPC decoder. In order to enhance the decoding throughput and reduce the size of memories storing soft messages, an improved early termination (ET) scheme and base matrix reordering technique is employed. These techniques significantly reduce the total number of decoding iterations and memory accessing conflicts without mitigating the decoding performance. Equipped with these techniques an area efficient and high throughput multi-rate QC-LDPC decoder is designed, simulated and implemented with Xilinx Virtex6 (XC6VLX760-2FF1760) for an irregular LDPC code of length 1944 and code rates (1/2-5/6) specified in IEEE 802.11n standard. With a maximum clock frequency of 574.136-587.458 MHz the proposed QC-LDPC decoder can achieve throughput in the range of 1.27-2.17 Gb/s for 10 decoding iterations. Furthermore, by using Cadence RTL compiler with UMC 130 nm VLSI technology, the core area of the proposed QC-LDPC decoder is found to be 1.42 mm2 with a power dissipation in the range of 101.25-140.42 mW at 1.2 V supply voltage.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 45, Issue 11, November 2014, Pages 1489-1498
نویسندگان
, ,