Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode

In this work, we discuss the origin and temperature dependence of various mechanisms behind the flow of leakage current in two topologies of TFET - basic TFET and pocket doped TFET. It is shown that the leakage current of pocket doped TFET shows relatively less variations with change in temperature when compared with MOSFET and basic TFET, and hence they can be deployed in low voltage temperature variation prone applications. But, this advantage of pocket-doped TFET is overshadowed by the huge sensitivity of its ON-state current towards variations in doping concentration at the tunnel junction. Hence, the fabrication of the TFET based circuits requires a negotiation with the yield and cost of the fabrication process. In order to mitigate this issue, we propose a hybrid TFET-CMOS based power gating technique. The hybrid technique utilizes a minimum number of TFETs to reduce the sleep mode leakage current, while enabling a temperature variation tolerant sleep mode at a supply voltage of 0.6 V.