کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
10364394 | 871615 | 2005 | 9 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Optimization of the VTÂcontrol method for low-power ultra-thin double-gate SOI logic circuits
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
Application of the VT-control method is studied in ultra-thin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n- and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10Â nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized VT-control method is a promising way for realizing low-power SOI logic circuits. Furthermore, the scalability of this technique is verified by extending the simulations to other generations of the ITRS roadmap.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 38, Issue 3, January 2005, Pages 505-513
Journal: Integration, the VLSI Journal - Volume 38, Issue 3, January 2005, Pages 505-513
نویسندگان
Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khakifirooz, Ali Afzali-Kusha,