کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
10364711 | 871787 | 2015 | 7 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories
ترجمه فارسی عنوان
تأثیرات قابلیت اطمینان حافظه های شارژ با مانع شارژ نانوسیم مانع از سرعت بالا 3 بیت / سلولی
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
چکیده انگلیسی
This study experimentally examines the reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories. Unique Schottky barrier junctions strongly enhance hot-carrier generation, ensuring high-speed multi-level programming at low gate voltages. However, strong injected gate currents might cause potential retention and endurance concerns when the programming voltage is beyond 9Â V. The effective number of deep-level traps is insufficient for capturing injected electrons, such that some electrons occupy shallower states, producing retention degradation after thermal stress. The charge-trapping layers are susceptible to additional trap generation under strong gate currents, leading to considerable threshold-voltage shifts after cycling stress. A compromise of cell characteristics exists between excellent reliability and high-speed programming in 3-bit/cell Schottky barrier nanowire cells. The application of sub-8-V multi-level programming can alleviate the potential reliability generated by strong injected currents, preserving a favorable cycling endurance and thermal retention in 3-bit/cell Schottky barrier nanowire charge-trapping cells.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Reliability - Volume 55, Issue 1, January 2015, Pages 74-80
Journal: Microelectronics Reliability - Volume 55, Issue 1, January 2015, Pages 74-80
نویسندگان
Wei Chang, Chun-Hsing Shih, Yan-Xiang Luo, Wen-Fa Wu, Chenhsin Lien,