A high-speed offset cancelling distributed sample-and-hold architecture for flash A/D converters

A 6-bit high-speed analog-to-digital converter was implemented utilizing a novel distributed sample-and-hold architecture capable of sampling and subtracting the input preamplifier's offset. This architecture offers substantial improvement in the high-speed operation of the converter. Compared to the prior-art, the effective number of bits improves 0.8 bit. The spurious free dynamic range improvement is over 12 dB. In addition the implemented technique uses half the number of capacitors compared to similar designs. The converter achieves over 5.2 bit resolution up to the Nyquist input signal frequency. A simple but effective design methodology is also presented.