کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
10364845 | 871851 | 2013 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure](/preview/png/10364845.png)
چکیده انگلیسی
A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using an energy-efficient tri-level based capacitor switching procedure is presented. The proposed switching procedure achieves 97.66% less switching energy when compared to the conventional method. The number of unit capacitors is reduced by a factor of 4 over that of conventional architecture as well. To make the power consumption of the comparator scale down with respect to the comparison rate, the fully dynamic comparator is used. Moreover, the dynamic logic circuit is implemented to further reduce the power of digital circuits. The ADC is implemented in a 0.18 μm 1P6M CMOS technology. At 1.0-V power supply and 200KS/s, the ADC achieves an SNDR of 60.54 dB and consumes 1.33 μW, resulting in a figure-of-merit (FOM) of 7.7 fJ/conversion-step. The ADC core occupies an active area of only 230Ã400 µm2.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 44, Issue 12, December 2013, Pages 1132-1137
Journal: Microelectronics Journal - Volume 44, Issue 12, December 2013, Pages 1132-1137
نویسندگان
Zhangming Zhu, Yu Xiao, Weitie Wang, Yuheng Guan, Lianxi Liu, Yintang Yang,